> LTspice says .... Given how soggy the bipolar ones are compared to the JFET onesThis may well be flawed models. Many BJT models are pessimistic about Early Effect. Many JFET models do not give honest conductances. It may be more like one order of magnitude, not two orders as your models are saying. (And some JFETs have very much lower plate resistance than these models give.)
And the AC impedance may be quite different from DC readings. And real hard to measure meaningfully.
Your "worst" is 18K DC and 180K AC. Relative to the ~~28R impedance of an AB BJT output stage, this is "very high", I would not sneer on this basis alone.
Worst dropout is 4V; as you say, I bet few 9V-18V systems will still be happy as V1 falls to 4V.
The Diode-bias has two points: the base-bias current is quite small, starving the 1N914s; and you tucked an LED into the collector which gives large dropout. It would "look better" with R7=3.3K and the LED taken away. (Note that you could reduce 3.3K to say 2.7K and put the LED in this loop.)
Emitter resistors under the 2N3904s might bump the plate resistance; also unless you are getting very well-matched '3904s then another 20mV-100mV of dead resistance might improve mirror consistency.
> a naive implementation of this CCS, which would have an LED per channel, and two waste paths
Use Red (1.6V) LED. Nail to negative rail, pull-up with say 3K or 10K. Two 2N3904 with ~~1K emitter resistors will pull-down 1mA each channel. Pull-down won't happen when node is within ~~1V of rail; but the main thing is to clean the small-signal 9V up from rail, not to stay perfect to within a half-dB of clipping.
Personally, I'd throw a dart.... but that would let the magic juice out of my PC's LCD display....
posted 02-09-2009 05:55 PM CST (US) 
